Published Papers

Verification and Integration of a Sub-Micron CMOS Process for CAD, 1993 Masters Thesis

Partitioning Under Timing and Area Constraints, 1997 IEEE International Conference on Computer Design (ICCD)

K-way Partitioning under Timing, Pin, and Area Constraints, 1997 IEEE International Conference on Innovative Systems in Silicon (ISIS)

Partitioning under Multiple Constraints, 1998 PhD Dissertation.

Clustering to Improve Bi-Partition Quality and Run Time, 1999 IEEE International Symposium on Circuits and Systems (ISCAS)

Design and Verification of a Processor Using VHDL, Verilog, SystemC, and C++, DVCon 04, Best Paper Award!!

Signed Arithmetic in Verilog 2001 – Opportunities and Hazards, DVCon 05

Dramatically Increase the Performance of SystemC Simulations, DVCon 07

A 2mW 400MHz RF Transceiver SoC in 0.18um CMOS Technology for Wireless Medical Applications, Proceedings of the 2008 IEEE Radio Frequency Integrated Circuits Symposium, Atlanta, GA, June 15-17, 2008

Get to ASICs Faster - A Novel Mixed Signal Design Methodology, DVCon 09

Design and Verification of an Image Processing CPU using UVM, DVCon 13

Verification Of An Image Processing Mixed Signal ASIC, DVCon 16

Chip-Level Verification of an RF ASIC with CustomSim/VCS, SNUG 2019


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